1. Field of the Invention
The present invention relates to flip flops and, more particularly, to a high speed, low power, minimal area double edge triggered flip flop.
2. Description of the Related Art
A rising edge triggered flip flop is a device which latches and holds the logic state of its data input signal when the rising edge of its clock input signal is detected.
Similarly, a falling edge triggered flip flop is a device which latches and holds the logic state of its data input signal when the falling edge of its clock input signal is detected.
Therefore, a double edge triggered flip flop is a device which latches and holds the logic state of its data input signal when the rising edge or the falling edge of its clock input signal is detected. Double edge triggered flip flops are commonly used in double data rate RAMs and in high speed bus interfaces.
FIG. 1A shows a circuit diagram which illustrates a conventional double edge triggered flip flop 100. As shown in FIG. 1A, flop 100 includes a clock inverter U1 whose input 110 is connected to an external clock signal CLK. The output of clock inverter U1 generates an inverted clock signal CLKZ.
Flop 100 also includes a first flip flop FF1 and a second flip flop FF2. Flop FF1 has a data input D1 which is connected to an external data input 112, receiving a data signal DATA. Flipflop FF1 also has a clock input C1 which is connected to external clock input 110, receiving a clock signal CLK. Furthermore, flop FF1 also has an output Q1 which generates a first flop output signal FFS.
Similarly, Flop FF2 has a data input D2 which is connected to external data input 112, receiving a data signal DATA. Flipflop FF2 also has a clock input C2 which is connected to the output of inverter U1, receiving an inverted clock signal CLKZ. Furthermore, flop FF2 also has an output Q2 which generates a second flop output signal SFS.
As further shown in FIG. 1A, flop 100 also includes a pair of 2-input AND gates U2 and U3, and a 2-input OR gate U4. AND gate U2 has an output, a first input connected to Q1, the output of flop FF1, and a second input 110, connected to external clock input CLK.
AND gate U3 has an output, a first input connected to Q2, the output of flip flop FF2, and a second input connected to the output of clock inverter U1, receiving the inverted clock signal CLKZ. OR gate U4 has a first input connected to the output of AND gate U2, a second input connected to the output of AND gate U3, and an output connected to external output 114, generating the flop output signal QOUT.
FIGS. 1B1-1B4 show timing diagrams which illustrate the operation of flop 100. As shown in FIGS. 1A and 1B1-1B4, the rising edge of the CLK input signal on external clock input 110 causes flop FF1 to latch the logic state of the data input signal DATA on external data input 112. When latched, the logic state of the first flop output signal FFS, generated by flip flop output Q1, matches the logic state of the data input signal DATA.
When the clock rises, the logic state of the data signal DATA, at data input D1, is transferred to output Q1 of flip flop FF1, determining the logic state of the first flop signal FFS. For example, if the data input signal DATA is a logic high when the rising edge of the clock signal CLK is detected, the first flop signal FFS will be set to a logic high.
Furthermore, the rising edge of the clock signal CLK on the second input of AND gate U2 enables AND gate U2 to pass the logic state of the first flop output signal FFS. At almost the same time, the second input of AND gate U3 receives the falling edge of the inverted clock signal CLKZ output from clock inverter U1. This falling edge disables AND gate U3, causing AND gate U3 to output a logic low.
The logic low output by AND gate U3 enables OR gate U4 to pass the logic state output by AND gate U2 to QOUT, the flop output signal. Thus, when the clock rises, the logic state of the data signal DATA is transferred to flip flop FF1 output Q1, which is in turn transferred through AND gate U2 and OR gate U4 to external output 114, determining the logic state of the flop output signal QOUT.
Similarly, the falling edge of the clock signal CLK, on external clock input 110, causes the rising edge of the inverted clock signal CLKZ to be output from clock inverter U1. The rising edge of the inverted clock signal CLKZ causes flip flop FF2 to latch the logic state of the DATA input signal at input 112. When latched, the logic state of the second flop signal SFS, at output Q2 of FF2, matches the logic state of the data input signal DATA. When the clock falls, the logic state of the data signal DATA at data input D2 is transferred to output Q2 of flip flop FF2, determining the logic state of the second flop signal SFS. For example, if the data signal DATA is a logic low when the rising edge of the inverted clock signal CLKZ is detected, then the second flop output signal SFS will be set to a logic low.
Furthermore, the rising edge of the inverted clock signal CLKZ on the second input of AND gate U3 enables AND gate U3 to pass the logic state of the second flop output signal SFS. At almost the same time, the second input of AND gate U2 receives the falling edge of clock signal CLK. This falling edge disables AND gate U2, causing AND gate U2 to output a logic low.
The logic low output by AND gate U2 enables OR gate U4 to pass the logic state output by AND gate U3 to QOUT, the flop output signal. Thus, when the clock falls, the logic state of the data input signal DATA is transferred to Q2, the output of flip flop FF2, which is in turn transferred through AND gate U3 and OR gate U4 to external output 114, determining the logic state of the flop output signal QOUT.
One of the drawbacks of flop 100 is that it consumes a large amount of silicon area and a large amount of power. As noted above, flop 100 requires two flip flops, two AND gates, one OR gate, and one inverter.
Furthermore, the clock-to-output delay of flop 100 is excessive because the worst case propagation path includes four logic elements. Thus, when the CLK signal falls, the flop output signal QOUT cannot change state until the CLK signal propagates through inverter U1, and the DATA signal propagates through flip flop FF2, AND gate U3, and OR gate U4.
Referring to FIGS. 1B1-1B4, delay time DL1 represents the time required for the CLK signal to propagate through inverter U1, plus the clock-to-data delay time required for the DATA signal to propagate through flop FF2.
Similarly, delay time DL2 represents the time required for the data signal to propagate through AND gate U3 and OR gate U4. Thus, at a delay time DL2 after delay time DL1, the logic state of the flop output signal QOUT will be determined.
From the foregoing discussion, it can be seen that the total clock-to-data output delay for flop 100 is equal to DL1+DL2, which is excessive. Thus there is a definite need for a double edge triggered flip flop which requires less propagation delay time, less power, and less silicon area.
The double edge triggered flip flop of the present invention reduces the following flop parameters: clock-to-output propagation delay, power dissipation and silicon area.
A flip flop in accordance with the present invention includes a first device which has a first input connected to a clock signal, a second input connected to a first data signal, and a first device output signal. The clock signal alternates between a first logic state and a second logic state.
The first device generates the first device output signal in response to the first data signal, when the clock signal is in the first logic state. Furthermore, the first device holds the logic state of the first device output signal in the state which is present when the clock signal transitions from its first logic state to its second logic state.
The flip flop of the present invention also includes a second device which has a third input connected to the clock signal, a fourth input connected to a second data signal, and a second device output signal. The second device generates the second device output signal in response to the second data signal, when the clock signal is in the second logic state. Furthermore, the second device holds the logic state of the second device output signal in the state that is present when the clock signal transitions from its second logic state to its first logic state.
The flip flop also includes a multiplexer which has a fifth input connected to the first device output signal, a sixth input connected to the second device output signal, a seventh input connected to the clock signal, and a flop output which generates a flop output signal.
The multiplexer sets the logic state of the flop output signal in response to the logic state of the first device output signal when the clock signal is in the second logic state, and sets the logic state of the flop output signal in response to the logic state of the second device output signal when the clock signal is in the first logic state.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings, which set forth an illustrative embodiment of the principles upon which the invention is based.